MCBSTM32EXL【PDF 581/995 页】BOARD EVALUATION FOR STM32F103ZE

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RM0008

Note:

Controller area network (bxCAN)

CAN filter FIFO assignment register (CAN_FFA1R)

Address offset: 0x214

Reset value: 0x00

This register can be written only when the filter initialization mode is set (FINIT=1) in the

CAN_FMR register.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

FFA27

FFA26

FFA25

FFA24

FFA23

FFA22

FFA21

FFA20

FFA19

FFA18

FFA17

FFA16

Reserved

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

FFA15

rw

14

FFA14

rw

13

FFA13

rw

12

FFA12

rw

11

FFA11

rw

10

FFA10

rw

9

FFA9

rw

8

FFA8

rw

7

FFA7

rw

6

FFA6

rw

5

FFA5

rw

4

FFA4

rw

3

FFA3

rw

2

FFA2

rw

1

FFA1

rw

0

FFA0

rw

Bits 31:28

Reserved, forced by hardware to 0.

Bits 27:0 FFA x : Filter FIFO assignment for filter x

The message passing through this filter will be stored in the specified FIFO.

0: Filter assigned to FIFO 0

1: Filter assigned to FIFO 1

Note: Bits 27:14 are available in connectivity line devices only and are reserved otherwise.

CAN filter activation register (CAN_FA1R)

Address offset: 0x21C

Reset value: 0x00

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

FACT27 FACT26 FACT25 FACT24 FACT23 FACT22 FACT21 FACT20 FACT19 FACT18 FACT17 FACT16

Reserved

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FACT15 FACT14 FACT13 FACT12 FACT11 FACT10 FACT9

FACT8

FACT7

FACT6

FACT5

FACT4

FACT3

FACT2

FACT1

FACT0

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 31:28

Reserved, forced by hardware to 0.

Bits 27:0 FACT x : Filter active

The software sets this bit to activate Filter x. To modify the Filter x registers (CAN_FxR[0:7]),

the FACTx bit must be cleared or the FINIT bit of the CAN_FMR register must be set.

0: Filter x is not active

1: Filter x is active

Note: Bits 27:14 are available in connectivity line devices only and are reserved otherwise.

Doc ID 13902 Rev 9

581/995

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